1. Field of the Invention
The present invention generally relates to a method of fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method of fabricating a field effect transistor having a metal-containing gate electrode.
2. Description of the Related Art
Microelectronic devices are generally fabricated on a semiconductor substrate as integrated circuits wherein various conductive layers are interconnected with one another to facilitate propagation of electronic signals within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor.
A CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the semiconductor substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region that is formed between drain and source regions beneath the gate dielectric. The gate dielectric comprises a thin (e.g., 10 to 50 Angstroms) material layer having a dielectric constant of about 4.0 or greater (e.g., silicon dioxide (SiO2), silicon oxynitride (SiON), hafnium dioxide (HfO2), and the like).
In advanced CMOS transistors, the gate electrode may be formed from at least one of a metal (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and the like) and metal-containing conductive compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and the like). Herein such a gate electrode is referred to as a metal-containing gate electrode. Generally, the metal-containing gate electrode comprises a top contact (e.g., doped polysilicon) to facilitate a low-resistance interface between the gate structure of the CMOS transistor and conductive lines of the integrated circuit. Replacement of polysilicon as a traditional material of the gate electrode with metals and metal-containing compounds reduces undesired voltage drop associated with the polysilicon depletion effect, as well as increases drive current performance and operational speed of the CMOS transistor.
Etch processes used during fabrication of the gate structures having metal-containing gate electrodes may have low etch selectivity to the underlying dielectric layers and, as such, damage the gate dielectric layer of the transistor. Additionally, the chemistries used to etch the polysilicon contact layer of the gate structure produce polymeric post-etch residue. Removal of the residue using conventional etchants (e.g., chlorine (Cl2), hydrogen bromide (HBr), and the like) is a difficult to control process that may also damage the thin gate dielectric layer, as well as contaminate a processing chamber of the etch reactor. Fabrication of the gate structures having metal-containing gate electrodes using such etch and residue removing processes generally has a low yield, as well as requires integration of additional processing equipment in the process flow that is conventionally used in the semiconductor fabs to fabricate field effect transistors, thus increasing the costs of manufacturing the microelectronic devices and integrated circuits.
Therefore, there is a need in the art for an improved method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode.